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PRELIMINARY
Z86228 CPS DC-4243-00
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
Z86228
LINE 21 CLOSED CAPTION CONTROLLER (L21C)
GENERAL DESCRIPTION
The Z86228 (Line 21 Closed-Caption Controller) is a single I.C. designed to provide the functional performance of a L21C Decoder module. This SuperintegrationTM VLSI device is completely self contained requiring only composite video, a horizontal timing signal as input and an external keyer (i.e., video switch between TV video and ClosedCaption video) to produce captioned video. The Z86228 uses a wired logic approach to perform the functions selected through its input control signals. It is fabricated using standard CMOS technology and designed to achieve the lowest possible cost. The Z86228 is intended for use in a set-top decoder or in any television receiver conforming to the NTSC standard. It is capable of processing and displaying all standard L21C format transmissions including the codes specified by the FCC "Report and Order" on GEN Docket No. 91-1, dated April 12, 1991. In addition, the device conforms to the Electronic Industry Association's Recomended Practice 608, which provides supplemental guidelines for the transmission of captions, text, and Extended Data Services (EDS) on NTSC Field 2. Extended Data Services (EDS) packets encoded on Field 2 , may be displayed in either of two screen formats. If and when PAL and SECAM TV standards define a protocol using the Line 21 format, this design will be readily convertible to that standard. The Line 21 Closed Captioning System The L21C system provides for the transmission of CAPTION information and other TEXT material as an encoded composite data signal. This is during the unblanked portion of Line 21, field 1, of the standard NTSC video signal. The video signal conforms to the Standard Synchronizing Waveform for Color Transmission given in Sub-part E, Part 73 of the FCC Rules and Regulations.
DC-4243-00
(2-18-94)
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PRELIMINARY
Z86228 CPS DC-4243-00
PIN DESCRIPTION
DONF/SEN NRESET BOX LUM R G B HFI VSS (Digital) 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 LNG/SCK CT/SDA NSIN VDD (Digital) VDD (Analog) HLF SSL CVI VSS (Analog)
18-Pin DIP Package Diagram
Pin No. 11
Signal Description Composite Video Input (CVI) Composite NTSC video, nominally 1.0V p-p,. band limited to 600 kHz. Circuit operates with signal variations between 0.7-1.4V p-p. It is recommended that this signal pin be driven by an emitter follower through a 0.1 F capacitor. Sync Slice Level (SSL) Capacitor (0.1F) to store sync slice level voltage. H Flyback Input (HFI) Horizontal sync input at CMOS levels, polarity independent. Typically derived from the H Flyback pulse or any other horizontal timing signal. H Loop Filter (HLF) Value to be specified VSS (Digital) Digital Ground Connect to system ground DONF/SEN Input (control) In Parallel Mode this input controls the Decoder On/Off function CMOS input with High = On, Low = Off. In Serial Mode this input is the Enable for serial data input. CT/SDA Input (control) In Parallel Mode this input selects the Data Channel to be processed (along with LNG). CMOS input with High=CAPTIONS, Low =TEXT. In Serial mode this input is serial data input.
Pin No. 2
Signal Description NRESET Master reset for the I.C. and must be used in the Parallel Control Mode. It may be tied High in the Serial Mode if reset is to be performed through the serial data stream. LAG/SCK Input (control) In Parallel Mode this input selects the Data Channel to be processed (along with CT). CMOS input High=LANGUAGE I, Low=LANGUAGE II. In Serial Mode this input is Serial Clock In. Box Output (Box) Active High, CMOS level "black box" keying signal for Caption/Text display area. Luminance Output (LUM) Active High, CMOS level signal. Character video luminance signal. Color signals, RGB Outputs Active High, CMOS level color character video for color receiver use. VDD Digital Power pin. Connect to +5V source. VDD Analog VSS Analog. Analog Ground. Connect to system ground. (NSIN) Input (Control) Selects the mode to be used in interpreting the signals on the three Control pins. High = Parallel Mode, Low = Serial Mode.
18
12
8
3
4
13 9 1
5, 6, 7
15 14 10 16
17
2
PRELIMINARY
Z86228 CPS DC-4243-00
Horizontal Timing
The timing of the output signals; Box, Luminance, and RGB is set so that the start of the leading box preceding the first displayable character cell will occur at 13.6*s. (*Value may be altered by a Mask change - consult factory.) This is after the midpoint of the leading edge of the horizontal sync pulse of the composite video signal measured at pin 11 of the Z86228. It is assumed that the delay through the low pass filter will be 220 ns (refererence Figure). There are two ways to execute a FULL RESET of the Z86228: 1. Hold NRESET Low for 100 ns. This stops all internal circuits. The part is static and the 100 ns is the worst case time for the NRESET signal to propagate through the various gates. 2. Send NRESET command through the serial interface. The result is the same as in number 1. FULL RESET is useful during power-up. A FULL RESET of the part during normal operation is not necessary. A partial reset may also be executed through the serial interface only. This is the COMMAND PROCESSOR RESET. Basically, all internal timing circuits continue to operate, but the caption display is removed from the screen and the Z86228 waits for new line 21 data. This is useful for situations such as channel change.
ABSOLUTE MAXIMUM RATINGS
Sym Vcc TSTG TA Description Supply Voltage* Storage Temp Oper Ambient Temp Min Max Units V C C Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
-0.3 +7.0 -65C +150 0 70
Notes: * Voltages on all pins with respect to GND.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin in Standard Test Load.
From Output Under Test
+5V
2.1 k
150 pF w 250 A
Standard Test Load
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PRELIMINARY
Z86228 CPS DC-4243-00
DC CHARACTERISTICS TA = 0C to +70C; VCC = +4.75V to +5.25V
Sym VIL VIH VOL VOH IIL ICC Parameter Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Input Leakage Supply Current Min 0 0.7VCC VCC-0.4 -.0 Max 0.2VCC VCC 0.4 1 3.0 25 Units V V V V V A mA Conditions
IOL = 1.00 mA IOL = 50 A [1] IOH = 0.75 mA [2] 0V, VCC [3]
Notes: [1] Pin 13 (HLF) [2] Pin 17 (CT/SDA) is Open-Drain. [3] VDD Digital + VDD Analog combined.
AC AND TIMING CHARACTERISTICS* (Reference Line 21 AC/DC Timing)
Composite Video Input Amplitude: 1.0 V p-p, 3 dB Polarity: Sync tips negative Bandwidth 600 kHz Horizontal Signal Input (preferably H Flyback) Amplitude: CMOS level signal, Low 0.2VCC, High 0.7VCC Polarity: Any Frequency: 15,734.263 Hz, 3% Line 211 Input Parameters (at 1.0 V p-p) Code Level: 50 IRE 10 IRE Clock Run-in Start 2: 10.5 s, 0.5s Input Signal-to-Random Noise Performance Unit will function down to a 25 dB ratio (CCIR weighted) with one error per row or better at that level. Internal Sync Circuits The internal sync circuits will lock to all 525 line signals having a vertical sync pulse that meets the following conditions: s It is at least 2.5H long. s It starts at the proper 2H boundary for its field. s If equalizing pulse serrations are present they must be less than 0.125H in width. Timing Signals Dot Clock: Dot Period: Character Cell Width: Width of Row (Box): Width of Row (Char):
768 x FH = 12.0839 MHz 82.75 nsec 1.324 sec 45.018 sec 42.370 sec
*All values are nominal and not fully characterized. 4
PRELIMINARY
Z86228 CPS DC-4243-00
AC/DC TIMING Line 21
Center of Active Video Cell Width = 1.324 s Log Ref "white" -100 IRE 2nd CHAR 32nd CHAR 1st CHAR -(100) IRE
Blanking 0 IRE -40 IRE
-(0) IRE -(40) IRE
CHAR LUM = 42.370 s BOX = 45.018 s 13.6s
35.73s Comp Video A 1 Z86228 LUM BOX R G B
LOW PASS FILTER
Line 21 AC/DC Timing
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PRELIMINARY
Z86228 CPS DC-4243-00
AC CHARACTERISTICS TA = 0C to + 70C; VCC = +4.75V to +5.25V
Tckd SEN Tckh Tckl Tenl
SCK Tout Toff Tdsu Tdh Tasu Tah Tout Toff
SDA
HI-Z
SS-OUT
HI-Z
D0-IN
D(1-7)-IN
A0-IN
HI-Z
SS-OUT
HI-Z
Serial Mode Timing Diagram
Symbol TOUT TOFF TCKD TCKL TCKH TDSU TDH TENI TASU TAH
Description Output enable time, ENA rising edge to Data Out Output disable time, CLK or ENA falling edge to Data Hi-Z Data read time, ENA rising edge to CLK low CLK low time CLK high time Data set-up time Data hold time ENA low time A0 set-up time A0 hold time
Min.
Max. 200 100
Units ns ns ns ns ns ns ms ns ns ns
200 200 200 100 100 200 100 100
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PRELIMINARY
Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specifcation requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-
Z86228 CPS DC-4243-00
stated on the front and back of the slaes order acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship.
conformance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues.
(c) 1994 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056
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